As a conventional high-withstand voltage semiconductor device, a power integrated circuit device (HVIC: High Voltage IC) in which a power semiconductor device and logic circuits are integrated on a single chip has been used to control the driving of various apparatuses, such as motors, lighting apparatuses and imaging apparatuses.
FIG. 44 is a plan view showing a conventional power integrated circuit device (hereafter simply referred to as an HVIC). FIGS. 45 to 48 are sectional views of the conventional HVIC shown in FIG. 44. FIG. 45 is a sectional view taken on line A-A′ of FIG. 44, FIG. 46 is a sectional view taken on line B-B′ of FIG. 44, and FIG. 47 is a sectional view taken on line C-C′ of FIG. 44. FIG. 48 is a block diagram showing the configuration of a high-side (high-potential-side) driver circuit of the conventional HVIC.
The HVIC shown in FIG. 44 comprises a high-withstand voltage N-channel MOSFET 100, a first logic circuit 200 connected to the gate electrode of the MOSFET 100 and a high-potential island 400 having a high-potential-side second logic circuit 300 connected to the drain electrode of the MOSFET 100. The high-potential island 400 is separated from other low-potential regions using a trench separation region 401, and the drain electrode of the MOSFET 100 is connected to the second logic circuit 300 using a high-potential level shift wire.
As shown in the sectional views of the HVIC, FIG. 45, FIG. 46 and FIG. 47, a buried oxide film 2 and an N−-type epitaxial layer 3 are formed on an N-type semiconductor substrate 1 (a P-type can also be used). As shown in FIG. 45, P+-type separation-diffusion regions 4 are formed so as to reach the buried oxide film 2 and enclose trench separation regions 16. In FIG. 45, FIG. 46 and FIG. 47, numeral 5 designates a deep N+-type diffusion region, numeral 6 designates a P diffusion region, numeral 7 designates a P+-type diffusion region, numeral 8 designates an N+-type diffusion region, numeral 9 designates a gate electrode also used as a field plate, numeral 10 designates an aluminum electrode also used as a GND-side field plate, numeral 11 designates an oxide film, numeral 12 designates a level shift aluminum electrode used as the level shift wire, and numeral 14 designates a field oxide film (LOCOS film). The HVIC has a separation structure, that is, a RESURF (Reduced Surface Field) structure, in which the N−-type epitaxial layer 3 is separated and enclosed using the trench separation regions 16 and the P+-type separation-diffusion regions 4 (for example, refer to U.S. Pat. No. 4,292,642). FIG. 48 shows a multi-trench separation region in the high-side (high-potential-side) driver circuit of the conventional HVIC in broken lines.
As shown in FIGS. 44 and 45, the conventional HVIC is configured that the level shift aluminum electrode 12 serving as a high-potential level shift wire crosses over the P+-type separation-diffusion regions 4 having the potential of the substrate and the P diffusion regions 6. Hence, the elongation of a depletion layer that is formed on the N−-type epitaxial layer 3 is hindered, whereby there is a problem of lowering the withstand voltage of the device.
This problem in the structure of the conventional HVIC is dealt with using an MFFP (Multiple Floating Field Plate) structure in which a field plate is formed on the PN junction using a gate electrode or the like to obtain the elongation of the depletion layer, field plates are formed multiply by floating, and the surface field is stabilized using capacitance coupling (for example, JP-A No. 5-190693).
However, in the case that the potential difference between the level shift aluminum electrode 12 serving as the high-potential level shift wire and an aluminum electrode 10 serving as the GND-side field plate is larger than the dielectric strength voltage of the oxide film 11 formed between these layers, the structure must be designed so that a region in which the level shift aluminum electrode 12 serving as the high-potential level shift wire and the aluminum electrode 10 serving as the GND-side field plate overlap does not exist. If they overlap, the GND-side field plate (aluminum electrode 10) in such a region must be cut off.
In the conventional semiconductor device, when the voltage required for the HVIC becomes high, there is a problem that equipotential lines are distorted owing to the fact that the GND-side field plate (the aluminum electrode 10) is not provided under the level shift wire and owing to the influence of the potential of the level shift wire, whereby field concentration occurs and the withstand voltage of the device is lowered as described above. Conventionally, for the purpose of relieving this problem, the oxide film 11 between the level shift aluminum electrode 12 and the aluminum electrode 10 is formed to have a thickness of 2.0 μm or more. However, this increase in the thickness of the oxide film 11 between the layers makes the production process complicated and raises the cost of the production. In addition, if the oxide film 11 between the layers is formed to have a large thickness, there is a disadvantage that microfabrication technology cannot be applied. Furthermore, the problem that the equipotential lines are distorted owing to the influence of the high potential of the level shift wire cannot be avoided. Hence, a structure having no level shift wire has been desired.